This invention relates to phase-locked loops (PLL""s), and more particularly to dual-loop PLLs with frequency shift.
Many electronic systems are synchronous or clocked. These systems may rely on accurate clocks to synchronize the timing of operations and data transfers. A crystal oscillator can be used to generate a clock at a base frequency, which is then divided or multiplied to create one ore more clocks with desired frequencies. External clock can be received and likewise divided or multiplied to produce internal clocks.
Clocks are typically generated from oscillator outputs using phase-locked loops (PLL""s). PLLs are one of the most widely use building blocks in digital systems today. FIG. 1 illustrates a typical PLL. Phase detector 10 receives a reference-clock input from an external oscillator or clock source. The phase and frequency of the reference clock is compared to the phase and frequency of a feedback clock generated by voltage-controlled oscillator (VCO) 14. The feedback clock can be the output clock generated by the PLL, or a divided-down derivative of the output clock from VCO 14 such as produced by feedback counter 16.
Phase detector 10 outputs up and down signals UP, DN when the phase or frequency of one input does not match the phase or frequency of the other input. These up and down signals cause charge pump 12 to add or remove charge from filter capacitor 20, which integrates the charge. As charge is added or removed through resistor 21 from filter capacitor 20, the voltage input to VCO 14 is increased or decreased. VCO 14 responds by increasing or decreasing the frequency of the output clock. The feedback clock to phase detector 10 is likewise changed by VCO 14.
As charge pump 12 adds or removes charge from filter capacitor 20, altering control voltage VCTL input to VCO 14, the phase and frequency of the feedback clock are adjusted until the reference clock is matched. Then phase detector 10 stops generating up and down signals to charge pump 12, until charge leaks off filter capacitor 20 or the reference clock changes.
Pulses of short duration are often used for up and down signals UP, DN. For example, phase detector 10 can be a pair of simple flip-flops. One flip-flop outputs the UP pulse when clocked by the reference-clock input. The UP pulse ends when cleared by the feedback-clock input. The other flip-flop generates the DN pulse when clocked by the feedback-clock input. The DN pulse ends when cleared by the reference-clock input. As the phases match more closely, the duration of the pulses shorten.
Often both up and down signals are pulsed simultaneously when little or no phase adjustment is needed. Charge pump 12 should supply either no charge or equal up and down charges to filter capacitor 20 so that a net zero charge is supplied when the duration of simultaneous UP and DN pulses are identical.
Sometimes the frequency of the reference clock shifts over time, either intentionally or unintentionally. Intention frequency shifts may occur as line conditions change, such as when a communications channel experiences better conditions and can handle a higher bit rate for a period of time.
Since clocks are intended to be stable, such frequency shifts may be difficult to track. The PLL may lose sync or otherwise produce erroneous results. The net charge added to filter capacitor 20 may not exactly compensate for the frequency shift, resulting in a phase error. VCO 14 may responds by slightly changing the phase and frequency of the feedback clock so that it no longer exactly matches the reference clock.
FIG. 2 is a timing diagram of UP and DOWN inputs to a charge pump and the resulting control voltage to the VCO when the reference frequency is shifted. When the frequency of the input reference clock is shifted upward, a leading phase difference is detected by the phase detector, and an UP pulse is generated. The charge pump responds to the UP pulse by pumping positive charge to the filter capacitor, increasing the control voltage VCTL to the VCO. The amount of charge pumped to the filter capacitor depends on the duration of the UP pulse. Once the frequency shift ends, the UP pulse ends, and the control voltage remains stable. Down pulses DN may also be activated during the shift when the frequency shift is relatively slow.
Ideally, the net current of the UP and DN pulses should match the frequency shift. The net charge added to the control voltage should exactly match the new frequency. This net charge added by the charge pump shifts the frequency of the VCO.
What is desired is a PLL that can smoothly respond to a shift in the input frequency. A PLL that can have a frequency offset is desirable. A frequency-shifting PLL is desirable.